Present complementary metal oxide semiconductor (CMOS) dynamic random access memory (DRAM) circuits are frequently used for main memory in a variety of applications including desk top and portable computer systems. The extensive use of dynamic random access memory circuits for low power applications requires low standby power consumption to prolong system battery life. The trend in dynamic random access memory design is to minimize power consumption of circuits such as reference supplies and bias circuit oscillators which operate during standby mode.
Previous memory circuits have employed reference circuits as disclosed in U.S. Pat. No. 5,208,776, entitled PULSE GENERATION CIRCUIT and issued to Nasu et al (FIG. 90) to reduce power consumption. Previous oscillator circuits used power saving techniques, as disclosed by Nasu et al in the oscillator (FIG. 112) and block diagram (FIG. 182a), that include a separate low power oscillator dedicated to standby operation. Such oscillator circuits may be used in dynamic random access memory circuits to drive substrate pump circuits, as shown by Nasu et al (FIG. 113). Nasu et al also disclose the use of a regulated internal supply voltage VPERI (FIG. 87), which is derived from an external supply voltage VEXT. The oscillator (FIG. 112) operates at the supply voltage VPERI to produce an output signal for driving the pump circuit of FIG. 113. Power consumed by the oscillator is equal to the product of internal supply voltage VPERI and current consumed by the oscillator. Thus, power consumption by the oscillator is reduced, because the magnitude of internal supply voltage VPERI is less than the magnitude of external supply voltage VEXT. However, a problem with this method is that pump circuit efficiency, which depends on the magnitude of the oscillator signal, is degraded.
Takashima et al describe an arrangement to reduce power consumed by production of internal voltage V.sub.int in Low-Power On-Chip Supply Voltage Conversion Scheme for 1G/4G bit DRAMs, 1992 Symposium on VLSI Circuits, Jun. 1992, pp.114-115, and Low-Power On-Chip Supply Voltage Conversion Scheme for Ultrahigh-Density DRAM's, IEEE J. Solid-State Circuits, vol. 28, no. 4, Apr. 1993, pp.504-508. Takashima et al teach operation of two series connected DRAM devices or two series connected halves of one DRAM between external voltage V.sub.ext and reference voltage V.sub.SS to produce internal voltage V.sub.int without the overhead of regulator power consumption. However, internal circuits, such as oscillators and their respective pump circuits, operate at one half of the magnitude of the external voltage V.sub.ext. Thus, a problem with this method is that pump circuit efficiency, which depends on the magnitude of the oscillator signal, is degraded.